(China (Mainland))
Product Summary
The XC5215-6PQ160C is the Field-Programmable Gate Array which is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA families, the XC5215-6PQ160C brings a robust feature set to programmable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5215-6PQ160C is delivered through the familiar Xilinx software environment. The XC5215-6PQ160C is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, VHDL, and Verilog HDL synthesis.
Parametrics
XC5215-6PQ160C absolute maximum ratings: (1)VCC Supply voltage relative to GND: -0.5 to +7.0 V; (2)VIN Input voltage with respect to GND: -0.5 to VCC +0.5 V; (3)VTS Voltage applied to 3-state output: -0.5 to VCC +0.5 V; (4)TSTG Storage temperature (ambient): -65 to +150 ℃; (5)TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm): +260 ℃; (6)TJ Junction temperature in plastic packages: +125 ℃; (7)Junction temperature in ceramic packages: +150 ℃.
Features
XC5215-6PQ160C features: (1)Low-cost, register/latch rich, SRAM based reprogrammable architecture; (2)0.5mm three-layer metal CMOS process technology; (3)256 to 1936 logic cells (3,000 to 23,000 gates; (4)Price competitive with Gate Arrays; (5)System Level Features; (6)System performance beyond 50 MHz; (7)6 levels of interconnect hierarchy; (8)VersaRingI/O Interface for pin-locking; (9)Dedicated carry logic for high-speed arithmetic functions; (10)Cascade chain for wide input functions; (11)Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins; (12)Internal 3-state bussing capability; (13)Four dedicated low-skew clock or signal distribution nets.
Diagrams
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